1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly relates to a semiconductor device and a manufacturing method thereof including a field effect transistor.
2. Description of the Related Art
In recent years, technical barriers to reduce a gate length of the field effect transistor are increasing. In order to alleviate the situation, attention is focused on high mobility channel materials, for example, strained Si, SiGe, Ge and the like. Additionally, it is known that, when the gate length is reduced, speed of carrier injection at a source end is more important rather than carrier mobility in operation speed of the transistor.
In a transistor disclosed in JP-A-2004-39762 (Patent Document 1), with regard to the source end, when carriers are moved from a Si-layer region to a Si1-xGex (x=0 to 1) layer region, a band gap between a conductor and a valence band is narrowed and thereby speed of carrier injection is increased. Patent Document 1 discloses that operation speed of the transistor can be improved as a result of the increase of carrier injection speed even when the gate length is short.
The transistor having the same structure is disclosed also in JP-A-2005-209980 (Patent Document 2). In Patent Document 2, extensions and deep source/drain regions are made of the Si layer because it is difficult to control impurity diffusion when the channel and the source/drain regions are all made of SiGe. Patent Document 2 discloses that channel mobility can be improved while maintaining controllability of impurity diffusion in the source/drain regions according to the structure.
In a transistor disclosed in JP-A-3-280437 (Patent Document 3), a SiGe layer is formed in the Si layer by Ge ion implantation, and the channel region has a structure in which a gate oxide film, the Si layer and the SiGe layer are stacked. According to the structure, carriers are moved in the SiGe layer having the narrow band gap and high mobility while forming the uniform gate oxide film, thereby improving transistor characteristics. This is a so-called SiGe channel transistor.
In JP-A-5-112491 (Patent Document 4), a double-gate transistor is disclosed, in which carrier are moved in SiGe. This is also the SiGe channel transistor similar to the Patent Document 3.
A transistor disclosed in Jp-A-2001-291864 (Patent Document 5) improves CMOS characteristics by forming tensile strained SiGe in the channel region and improving drive current of an NMOS and a PMOS in a balanced manner. The transistor disclosed in Patent Document 5 is also the SiGe channel transistor.
In the case of tensile Si, drive current is improved 1.7 times in the NMOS and 1.4 times in the PMOS as much as the drive current in the MOSFET made of Si. As a result, unbalance between the NMOS and the PMOS further increases. Therefore, it is necessary to improve the rate of improvement in drive current of the PMOS. The rate of improvement in mobility is higher than the tensile Si in a region having higher Ge concentration when using the tensile SiGe, therefore, the CMOS characteristics can be improved.
However, the transistor disclosed in Patent Document 1 has a structure in which the SiGe region is extended to ends of the gate. Normally, an extension impurity is designed so as to enter the inside of the gate to form overlap regions. That is, in the transistor structure of Patent Document 1, junctions of the source/drain are formed in the SiGe region, therefore, it is difficult to suppress junction leakage due to the narrower band gap as compared with Si. As a result, the junction leakage leads to increase of off-leakage current and characteristics as an LSI will deteriorate.
The transistor of Patent Document 2 has a structure in which the gate is arranged to the outside of the SiGe region formed in advance so that impurities do not enter the SiGe region in the light of controllability of impurity profiles. In Patent Document 2, a depletion layer of the extension may enter the SiGe region. In this regard, the junction leakage similar to Patent Document 1 may occur. Additionally, the gate is formed after the SiGe region is formed in the process, therefore, the process is not self aligned. As a result, the source/drain junctions are not always formed outside the SiGe region and the junction leakage may occur in the same manner as Patent Document 1.
In the cases of Patent Documents 3 to 5, as whole the source/drain regions are SiGe regions, the transistor has a structure in which the junction leakage is more likely to occur than Patent Document 1, which may leads to increase of off-leakage current.